In the device test of a semiconductor memory device, the various memory cells must have the prescribed value as their stored information. However, when the power source is turned on, the value becomes undetermined for each memory cell. Consequently, before performing the test, it is necessary to initialize the semiconductor memory device by writing a prescribed datum (0 or 1) into all of the memory cells. For conventional semiconductor memory devices, such as one of the DRAM type, the memory cell region is divided into multiple memory blocks known as memory cell arrays. Consequently, initialization has to be performed for each memory cell array respectively.
FIG. 5 is a diagram illustrating a typical configuration of a DRAM memory cell array. In this figure, for simplifying the explanation, the array size is schematically represented by 16 columns (X-address) and 8 rows (Y-address). In this memory cell array, for each row a pair of complementary bit lines BLi, BLi- are connected via transfer gates TR1 and TR2 to a differential sense amplifier SAi and a precharge circuit PRi arranged for the row. At the cross points between one bit line BLi and even-numbered word lines WL0, WL2, . . . WL14, memory cells in the even-numbered columns MCi,0, MCi,2, . . . MCi,14 are connected. On the other hand, at the cross points between other bit line BLi- and odd-numbered word lines WL1, WL3, . . . WL15, memory cells in the odd-numbered columns MCi,1, MCi,3, . . . MCi,15 are connected, and the overall memory cell array has 8 rows.times.16 columns of memory cells arranged in a matrix configuration. Each memory cell MCi,j comprises one transistor and one storage capacitor.
With respect to FIG. 6, the data read/write operation into the memory cells of this memory cell array can be explained. As far as the standby state before the read/write operation is concerned, the equalization control signal .phi.E is at the high (H) level, and transistors TR3, TR4, TR5 of precharge circuit PRi of each row are ON. A voltage of Vcc/2 is applied to precharge voltage feed line BLR. From this voltage feed line BLR, bit lines BLi, BLi- of each line are precharged with a voltage of Vcc/2 via transistors TR3, TR4, TR5. When external row address strobe signal RAS- falls to the low L level for read/write operation, equalization control signal .phi.E correspondingly assumes the L-level, and transistors TR3, TR4, TR5 of precharge circuit PRi of each row are turned OFF. Then, word line WLj of the selected column is activated, and the potential of the bit line (such as BLi-) varies corresponding to the stored information in the various memory cells MC0,j, MC1,j, . . . MC7,j connected to said word line WLj. In the example shown in FIG. 6, the stored information is "0," and the potential of bit line BLi- changes a little from the level of Vcc/2 to the lower side.
Then, while one sense amplifier driving signal NC is pushed down to Vss (L-level voltage), the other sense amplifier driving signal PC is pulled up to Vcc (H-level voltage). Corresponding to this change, for sense amplifier SA of each row, the bit line potential is amplified to the potential of the digital logic so that one of the bit line pair BLi, BLi- is pushed down to Vss, while the other is pulled up to Vcc. At this time, since signal .phi.T is at the high level, transistors TR1, TR2 are in ON state, and the bit line pair BLi, BLi- is connected to sense amplifier SAi. In the example shown in FIG. 6, since the stored information of the memory cell connected to bit line BLi- is "0", bit line BLi- is pulled down to Vss (L-level voltage). On the other hand, bit line BLi is pulled up to Vcc (H-level voltage).
Then, in the row selected by Y-address, Y-address line YSi is activated, so that transfer gates TR6, TR7 of the row are turned ON, and sense amplifier SAi of the row is connected to data input/output line I/O. In this way, in the case of write operation, the datum from data input/output line I/O is sent to bit line BLi- through transistor TR6, sense amplifier SAi and transfer gate TR1, and it is written into memory cell MCi,j at the intersection of bit line BLi- and word line WLj. In the case of read operation, the datum read from memory cell MCi,j to bit line BLi- is sent out to data input/output line I/O through transfer gate T1, sense amplifier SAi, and transistor gate TR6.
In order to perform initialization for the aforementioned memory cell array, the following three methods have been heretofore adopted.
(1) Initialization by means of a normal write operation PA1 (2) Initialization by means of a parallel write operation PA1 (3) Initialization by means of a test operation (column or row copy mode)
In the initialization by means of the normal write operation, the aforementioned write operation is carried out for all of the memory cells. Consequently, for the memory cell array shown in FIG. 5, the write cycle is repeated 16.times.8 times. For the overall memory device, the number of the write cycles that have to be performed corresponds to the volume of the memory device. For example, for a 64 Mbit memory, it is necessary to perform 64.times.10.sup.6 write cycles.
In the initialization by means of the parallel write operation, in the aforementioned write operation, after driving of sense amplifiers SA0-SA7 of each row, for the row selected by the Y-address, such as row 0, multiple (such as two) Y-address lines YS0, YS4 are selected in parallel, and data are written into the two memory cells MC0,j, MC4,j in parallel (at the same time). Consequently, compared with the scheme of initialization by means of normal write operation, the number of write cycles can be halved.
In the method of initialization by means of the test operation, first of all, the normal operation or parallel-write operation is performed so that the data are written into all of the memory cells MC0,0, MC1,0, . . . MC7,0 connected to a word line, such as column 0 word line WL0. Then, it enters the test operation mode by means of control using WE/CAS-before-RAS [control], etc. In the test operation mode, the stored data in memory cells MC0,0, MC1,0, . . . MC7,0 connected to word line WL0 are read to bit lines BL0, BL1, . . . BL7, respectively. The read stored data are latched in sense amplifiers SA0-SA7 of each row, respectively. Then, while driving of various sense amplifiers SA0-SA7 is continued, the X-addresses of the even-numbered columns of column 2 through column 14 are scanned, and word lines WL0, WL2, . . . WL14 are sequentially activated, and sequential write operation is performed so that the stored data of column 0 are copied to the other even-numbered columns. Then, the same operation is repeated for the odd-numbered columns. That is, first of all, the data are written into all of the memory cells in column 1, MC0,1, MCI,1, . . . MC7,1; then, these stored data in column 1 are copied in sequence to the memory cells of the other odd-numbered columns via sense amplifiers SA0-SA7 and bit lines BL0-, BLI-, . . . BL7- of each row.
However, in the device testing of recently developed semiconductor memory devices, there is a demand to shorten the test time as the memory volume is increased, and hence there is a demand to shorten the time for initialization. All of the conventional methods, however, fail to meet this demand for shortening the initialization time.
In particular, for the initialization method using the normal write operation, as the number of the develop cycles is equal to the number of the memory cells, a long time is needed.
For the initialization method using the parallel write operation, although the time needed in this case can be halved or even reduced to a small fraction with respect to the time needed in the initialization method using the normal write operation, there is nevertheless a limit on the ratio corresponding to the parallel number, and the time cannot be further shortened.
In this respect, for the initialization operation using the test operation, since the data written into the memory cells of one column are copied to the memory cells of the other columns, the time-shortening effect is significant. However, even in this case, it is necessary to perform the read/write operation in two rounds for the memory cells in the even-numbered columns connected to bit lines BL0, BL1, . . . BL7 and for the memory cells in the odd-numbered columns connected to bit lines BL0-, BLi-, . . . BL7-, respectively. Also, in recently developed DRAMs, in order to prevent noise caused by parasitic capacitance among the bit lines, a twist configuration is usually adopted. In this configuration, the complementary bit lines BLi, BLi- of each row are twisted once after a prescribed distance so that their positions are exchanged. In this configuration, the connection configuration between the bit line and the word line is inverted at each twist site. Consequently, in order to write the same datum (physical logic value) into all of the memory cells, it is necessary to perform the write/transfer operation for each divided twist region, respectively. As a result, control becomes very complicated, and the effect in shortening the time becomes less significant. This is a disadvantage.